Memory devices are used in many applications, such as computers, calculators, and cellular phones, as examples. Memory devices may be non-volatile or static, or they may be dynamic, requiring refreshing periodically. One type of dynamic memory device is a dynamic random access memory (DRAM) device, in which bits of data are stored in capacitors of an integrated circuit. DRAM devices are often arranged in square or rectangular arrays of memory cells, each having one capacitor and one transistor. DRAM devices may be thousands of cells in length and width, and may comprise millions of cells on a single DRAM chip.
FIG. 1 illustrates a known DRAM chip 100 architecture. The DRAM chip 100 includes a substrate having eight memory banks 102, e.g., bank0 through bank7. Each memory bank 102 comprises a number of memory cells 104, including cell 104a and 104b in bank 0 and bank6, respectively. Control signal pads 106 and input/output pads 108 are formed on a central spine 110 of the DRAM chip 100 between the memory banks 102. The DRAM chip 100 has a mixture of a number of control signal pads 106 and data input/output pads 108 located in the same central spine 110 region of the chip 100. The length dimension d1 of the DRAM chip 100 may be about 12-22 mm, and the height dimension d2 of the DRAM chip 100 may be about 9-10 mm, as examples. The central spine 110 may have a width dimension d3 of about 0.2-0.6 mm, for example.
To read or write to one of the memory cells 104 in the memory banks 102, control signals are input to control signal pads 106, and the information is read from or written to a memory cell 104. For example, to read a memory cell 104a in memory bank 102 of bank0, a control signal 112a (e.g., a CMD/ADDRESS) is sent from a control signal pad 106 in the central spine 110 to the cell 104a. The state of the cell 104a is read, and the information is returned as a data signal 114a to the central spine 110 and along the central spine 110 to a data output pad 108 on the right edge of the DRAM chip 100. Likewise, to read a memory cell 104b in a memory bank 102 of bank6, a control signal 112b is sent from a control signal pad 106 in the central spine 110 to the memory cell 104b. The state of the memory cell 104b is read, and the information is returned as a data signal 114b to the central spine 110 and along the central spine 110 to the data input/output pad 108 on the right edge of the DRAM chip 100.
A problem with the DRAM chip 100 architecture shown in FIG. 1 is that the speed of accessing the memory cells 104 varies depending on the location of the memory banks 102 and the location of the memory cells 104 within the memory banks 102. For example, accessing memory cell 104b is much faster than accessing memory cell 104a because the access length is smaller. The worst case total access length to access memory cell 104a in bank0 is about (1.5*d1+d2), and the best case total access length to access memory cell 104b in bank6 is about (0.5*d1) for the DRAM chip 100 shown. The difference in the worst and best case total access length of the DRAM chip 100 is about (d1+d2).
Thus, the DRAM chip 100 architecture has several disadvantages, including a large worst case access length and a large total access time. There also is a large difference between the worst case and best case total access length, which requires a large effort in other portions of the DRAM chip 100 to compensate for the difference in the worst case and best case total access length. The compensation circuitry may include a latency counter that requires high power consumption, for example.
FIG. 2 is a perspective view and FIG. 3 is a top view of a known board-on-chip (BOC) 120 packaging technique for a DRAM chip 100 shown in FIG. 1. The DRAM chip 100 is placed face down and is coupled to a substrate 122 or board having a slot 124 therein. The slot 124 is an aperture in the substrate 122 allowing access to the center spine 110 of the DRAM chip 100 that contains the address and control signal bond pads 106 and the data input/output bond pads 108. The substrate 122 includes a number of bond pads 126 at two edges of the slot 124, as shown in FIG. 3. (For simplicity, the bond pads and solder balls are not illustrated in FIG. 2.) The bond pads 106/108 of the DRAM chip 100 are attached to the bond pads 126 of the substrate 122 using bond wires 130 that extend through the slot 124 in the substrate 122. The substrate 122 includes a number of solder balls 128 to which the bond pads 126 are electrically coupled to using conductive traces or wiring (not shown) in or on the substrate 122.
Next generation high speed memory products are expected to operate at frequencies that cannot be handled using known memory design architectures such as those shown in FIGS. 1 through 3. The data path routing on the DRAM chip 100, on the package 120, and on memory modules on which the package 120 is mounted are too long and lack load matching, which limits the bandwidth.
Thus, what are needed in the art are improved memory chip architectures and packaging techniques.